1. Technical Field of the Invention
The present invention relates to programmable logic devices (PLDs), and particularly to PLDs that may be fabricated more simply and less expensively.
2. Description of the Related Art
Programmable logic devices (PLDs) have been in existence for some time. A conventional PLD may include a plurality of PLD cells, each of which is programmable/erasable into any of at least two states. Some conventional PLD cells utilized the EEPROM technology in which a programmable thin oxide capacitor conducts a small current when a sufficient voltage is applied across the oxide. The tunnel oxide is used to inject or extract charge from a floating gate connected to a sense transistor, which itself senses the programmed state of the thin oxide capacitor. Two additional transistors (a program transistor and a read transistor) and a control capacitor are included in this EEPROM-based PLD cell.
In part due to the rather sizable space occupied by the above-described EEPROM-based PLD cell, other technologies have been employed to provide a more compact PLD cell. The flash memory process has been utilized in PLDs. In a flash-based PLD cell, a flash floating gate transistor forms the programmable component. The flash-based PLD cell further includes a series-select transistor connected in series with the floating gate transistor. The gate/control terminal of the select transistor is coupled to a word line which selects or activates the PLD cell. The transistors in the conventional flash-based PLD cell (the select transistor and the flash floating gate transistor) are disposed adjacent each other on a PLD chip. Flash-based PLD cells offer increased density while being relatively compatible with leading nonvolatile memory technologies.
A shortcoming with conventional flash-based PLDs concerns integrating the flash floating gate transistor with a regular select transistor in an integrated circuit chip. In particular, there is a different process flow for fabricating the floating gate transistor relative to the process flow for fabricating the select transistor. Reliability issues relating to defectivity and tunnel oxide integrity have been experienced at each transition of a flash floating gate transistor and an adjacent regular select transistor.
Based upon the foregoing, there is a need for a reliable PLD cell that is fabricated in a cost effective manner and provides relatively high cell density.